Task C: Evaluation and Re-design | MURI: Universal Security Theory for Evaluation and Design of Nano-scale Devices and for Development of Innovative Security Primitives

With the data collected, and the models and compositions developed in Tasks A and B, in this task, (1) new nano-devices based on nano-CMOS, PCM, and 3D technology with security as the prime objective, and (2) new security primitives/enhancements shall be developed. Fabrication and simulation of these device concepts, security primitives, and compositions to validate the proposed metric using experimental analysis is one of the plans on this task.

Task C.1. New Nano-Devices and Architectures with Security in Mind
After understanding the universal properties S={S1, S2,…}, in this task, new devices with these properties in mind will be developed to strengthen the security primitives or weaken the success of attacks.In this task, the development of new devices (PCM, CMOS, PCM+CMOS, ±3D) will be investigated that (1) require negligible difference in terms of power when they are in (or transitioning between) different states (reduced observability), (2) experience no aging in case of PUF and TRNG (reduced controllability) [51] or rapid aging in case of CDIR (increased controllability) in the field [30], (3) inherently experience more physical variability [53,54] (increased controllability, reduced observability), (4) keep history of their previous reads or writes (tamper evidence), (5) offer a large challenge space (reduced observability), etc.

Task C.2. New Classes of Security Primitives and Attacks
In this task, development of new security primitives from 3D integration, nano-CMOS, PCM, and/or a combination of these technologies will be investigated. We shall utilize our taxonomy of universal security properties S of primitives and unique features U of devices such as: (1) storing device’s state history for built-in tamper evidence, (2) manufacturability features for enhancing observability and HW unclonability (used in strong PUFs and TRNGs), (3) low controllability in 3D structures for anti-reverse engineering, and (4) exploiting heterogeneous system integration via 3D for improving security. We shall also investigate new classes of attacks including Trojan attacks in 3D ICs, reliability attacks (i.e. latent attack, aging attack), etc.