Publications

2018

  1. Chakraborty, Y. Xie, and A. Srivastava, “GPU Obfuscation: Attack and Defense strategies,” Proceedings of the 55th Annual Design Automation Conference, pp.122, 2018.
  2. Y. Xie, and A. Srivastava. “Anti-SAT: Mitigating SAT Attack on Logic Locking.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2018).
  3. Y. Liu, Y. Xie, and A. Srivastava. “Security in Emerging Fabrication Technologies.” In Security Opportunities in Nano Devices and Emerging Technologies, CRC Press, 2018.
  4. Y. Liu, Y. Xie, C. Bao, and A. Srivastava. “A Combined Optimization-Theoretic and Side-Channel Approach for Attacking Strong Physical Unclonable Functions.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 1 (2018): 73-81.
  5. Y. Liu, Y. Xie, and A. Srivastava. “Neural trojans.” In Computer Design (ICCD), 2017 IEEE International Conference on, pp. 45-48. IEEE, 2017.
  6. C. Jin, C. Herder, L. Ren, P. H. Nguyen, B. Fuller, S. Devadas, and M. van Dijk, “FPGA Implementation of a Cryptographically-Secure PUF Based on Learning Parity with Noise,” Cryptography 1(3): 23 (2017) available at http://www.mdpi.com/2410-387X/1/3/23
  7. P. H. Nguyen, D. P. Sahoo, C. Jin, K. Mahmood, U. Ruhrmair, and M. van Dijk, “The Interpose PUF: Secure PUF Design against State-of-the-Art Machine Learning Attacks,” https://eprint.iacr.org/2018/350.pdf
  8. L. M. Nguyen, P. H. Nguyen, M. van Dijk, P. Richtárik, K. Scheinberg, and M. Takác, “SGD and Hogwild! Convergence Without the Bounded Gradients Assumption,” ICML 2018
  9. Y. Gao, C. Jin, J. Kim, H. Nili, X. Xu, W. Burleson, O. Kavehei, M. van Dijk, D. Ranasinghe, and U. Ruhrmaier, “Efficient Erasable PUFs from Programmable Logic and Memristors,” https://eprint.iacr.org/2018/358.pdf
  10. C. Jin, S. Valizadeh, and M. van Dijk, “Snapshotter: Lightweight intrusion detection and prevention system for industrial control systems,” ICPS 2018
  11. Y. Gao, M. van Dijk, L. Xu, S. Nepal, and D. C. Ranasinghe, “TREVERSE: TRial-and-Error Lightweight Secure ReVERSE Authentication with Simulatable PUFs,” https://arxiv.org/pdf/1807.11046.pdf
  12. A. Gorbenko*, N. Noor*, S. Muneer, R. S. Khan, L. Adnane, F. Dirisaglik, A. Cywar, B. Shakya, M. V. Dijk, A. Gokirmak and H. Silva, “Resistance drift and crystallization in suspended and on-oxide phase change memory line cells”, IET Electronics Letters (submitted, July 2018). (*Equal contribution)
  13. N. Noor, S. Muneer, R. S. Khan, A. Gorbenko, L. Adnane, F. Dirisaglik, A. Cywar, and H. Silva, “Reset Variability in Phase Change Memory for Hardware Security Applications”, IEEE Trans. Elec. Dev. (under revision, August 2018).
  14. S. Muneer, J. Scoggin, F. Dirisaglik, L. Adnane, A. Cywar, G. Bakan, K. Cil, C. Lam, H. Silva, and A. Gokirmak, “Activation energy of metastable amorphous Ge2Sb2Te5 from room temperature to melt”, AIP Advances 8 (6), 065314, 2018.
  15. J. Scoggin, R. S. Khan, H. Silva, and A. Gokirmak, “Modeling and impacts of the latent heat of phase change and specific heat for phase change materials”, Applied Physics Letters 112, 193502, 2018.
  16. Z. Woods, J. Scoggin, A. Cywar, L. Adnane, and A. Gokirmak “Modeling of Phase Change Memory: Nucleation, Growth and Amorphization Dynamics during Set and Reset: Part II – Discrete Grains,” IEEE Trans. Elect. Dev. 64, 11, 4472-4478, 2017.
  17. N. Noor, V. Manthina, S. Muneer, A. Agrios, A. Gokirmak, and H. Silva, “ZnO Nanoforest Optical PUF”, Materials Research Society Fall Meeting, 2018.
  18. J. Scoggin, H. Silva, and A. Gokirmak, “A finite element model of grain boundary melting in phase change memory devices based on thermodynamic principles”, Materials Research Society Fall Meeting, 2018, TP.04
  19. N. Noor, L. Sullivan, R. S. Khan, S. Muneer, F. Dirisaglik, Y. Zhu, A. Gokirmak, and H. Silva, “Variability Analysis of the Length of Amorphized Volume in phase change memory (PCM) line cells”, Materials Research Society Spring Meeting, 2018.
  20. A. Gorbenko, N. Noor, S. Muneer, R. S. Khan, F. Dirisaglik, A. Cywar, Y. Zhu, A. Gokirmak, and H. Silva, “Resistance Drift in Suspended and On-Oxide Gb2Se2Te5 Phase Change Memory Line Cells”, Materials Research Society Spring Meeting, 2018.
  21. R. S. Khan, Z. Woods, J. Scoggin, H. Silva, and A. Gokirmak, “Finite Element Modeling of Resistance Drift in Phase Change Memory Devices,” Material Research Society Spring Meeting, 2018, EP07.03.06.
  22. S. Muneer, J. Scoggin, L. Adnane, F. Dirisaglik, A. Cywar, R. S. Khan, Y. Zhu, C. Lam, H. Silva, and A. Gokirmak, “Temperature Dependent Resistivity, Conduction Activation Energy and Seebeck Coefficient of Metastable Amorphous Ge2Sb2Te5”, Material Research Society Spring Meeting, 2018, EP07.10.04.
  23. J. Scoggin, H. Silva, and A. Gokrimak, “Specific Heat, Heat of Crystallization and Heat of Fusion in Phase Change Memory – A Unified Model for Finite Element Simulations”, Materials Research Society Spring Meeting, 2018, EP07.10.05.
  24. J. Scoggin, Z. Woods, H. Silva, and A. Gokirmak, “Dimensionality: Balancing Accuracy and Complexity in Finite Element Simulations of Phase Change Memory and Ovonic Switching Devices”, Materials Research Society Spring Meeting, 2018, EP07.01.02.
  25. N. Noor, S. Muneer, L. Adnane, R. S. Khan, A. Gorbenko, F. Dirisaglik, A. Cywar, C. Lam, Y. Zhu, A. Gokirmak, and H. Silva, “Utilizing Programming Variability in Phase Change Memory Cells for Security”, Materials Research Society Fall Meeting, 2018.
  26. S. Muneer, H. Silva, and A. Gokirmak, “Simulations of Reset Operation of Phase Change Memory Devices Based on Semiconductor Physics including the Generation-Transport-Recombination (GTR) of Minority Carrier”, Material Research Society Fall Meeting, 2017, EM07.07.04.
  27. N. Noor and H. Silva, “Phase Change Memory for Physical Unclonable Functions”, submitted, in ‘Advanced Applications of Emerging NVM Devices’ ed. M. Suri , Springer 2018.
  28. R. Khan, N. Noor, J. Scoggin, C. Lu, M. vanDijk, A. Gokirmak, H. Silva, Phase-change memory and its applications in hardware security, in Security and Nano-Scale Devices, CRC Press / Taylor & Francis, USA, 2017
  29. A. Stern, U.J. Botero, B. Shakya, H. Shen, D. Forte, M. Tehranipoor, “EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked ICs”, to appear IEEE International Test Conference (ITC), October 2018.
  30. K. Yang, U.J. Botero, H. Shen, D. Woodard, D. Forte, M. Tehranipoor, “UCR: An Unclonable Environmentally-Sensitive Chipless RFID Tag For Protecting Supply Chain”, to appear ACM Transactions on Design Automation of Electronic Systems (TODAES), 2018.
  31. H. Shen, N. Asadizanjani, M. Tehranipoor, D. Forte, “Nanopyramid: An Optical Scrambler Against Backside Probing Attacks”, to appear International Symposium for Testing and Failure Analysis (ISTFA), October 2018.
  32. E. Principe, N. Asadi, D. Forte, R. Chivas, M. DiBattista, and S. Silverman, “Plasma FIB Deprocessing of Integrated Circuits from the Backside,” Electronic Device Failure Analysis (EDFA), 2018.
  33. O. Arias, F. Rahman, M. Tehranipoor, and Y. Jin, “Device Attestation: Past, Present, and Future,” Design Automation, and Test in Europe (DATE), 2018
  34. B. Shakya*, X. Xu*, M. Tehranipoor, D. Forte, “Bypass attack on SAT-resistant logic locking and comprehensive countermeasures,” IEEE Transactions on Computers (TComp), April 2018 (Submitted)
  35. F. Rahman, B. Shakya, X. Xu, D. Forte, M. Tehranipoor, “Security Beyond CMOS: Fundamentals, Applications, and Roadmap”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, No. 12, December 2017.
  36. H. Shen, F. Rahman, B. Shakya, X. Xu, M. Tehranipoor, D. Forte, “Poly-Si Based Physical Unclonable Functions”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, No. 11, November 2017.
  37. E.L. Principe, N. Asadi, D. Forte, M. Tehranipoor, R. Chivas, M. DiBattista, S. Silverman, “Plasma FIB Deprocessing of Integrated Circuits from the Backside”, Electronic Device Failure Analysis (EDFA), Vol. 19, No. 4, November 2017.
  38. H. Wang, Q. Shi, D. Forte, M. Tehranipoor, “Probing Attacks on Integrated Circuits: Challenges and Research Opportunities”, IEEE Design & Test, Vol. 34, No. 5, October 2017.
  39. S. Chowdhury, X. Xu, M. Tehranipoor, D. Forte, “Aging Resistant RO PUF with Increased Reliability in FPGA”, International Conference on Reconfigurable Computing and FPGAs (ReConFig), December 2017.
  40. E.L. Principe, N.Asadizanjani, D. Forte, M. Tehranipoor, R. Chivas, M. DiBattista, S.Silverman, M. Marsh, N. Piche, J. Mastovich, “Steps Toward Automated Deprocessing of Integrated Circuits,” International Symposium for Testing and Failure Analysis (ISTFA), November 2017.
  41. Z. Guo, X. Xu, M. Tehranipoor, D. Forte, “SCARe: An SRAM-based Countermeasure Against IC Recycling Framework”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 26, No. 3, April 2018.
  42. X. Xu, S. Keshavarz, D. Forte, M. Tehranipoor, D.E. Holcomb, “Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018.
  43. M. Sadegh Riazi, S.U. Hussain, F. Koushanfar: SHAIP: Secure Hamming Distance for Authentication of Intrinsic PUFs. ACM Transactions on Design Automation of Electronic Systems (TODAES) to appear.
  44. Riazi, S. M., M. Samragh, and F. Koushanfar, “CAMsure: Secure Content-Addressable Memory for Approximate Search”, ACM Transactions on Embedded Computing Systems (TECS), 2017.
  45. B.D. Rouhani, M. Samragh, M. Javaheripi, T. Javidi, and F. Koushanfar: Real-time and Assured Deep Learning: Practical Defense Against Adversarial Attacks, International Conference on Computer Aided Design (ICCAD) 2018.
  46. M. Sadegh Riazi, F. Koushanfar: Privacy-Preserving Deep Learning and Inference, International Conference on Computer Aided Design (ICCAD) 2018.

2017

  1. M. Tehranipoor, D. Forte, G, Rose, and S. Bhunia, Security Opportunities in Nano Devices and Emerging Technologies, CRC Press, 2017.
  2. N. Noor, S. Muneer, L. Adnane, RS Khan, A. Gorbenko, F. Dirisaglik, A. Cywar, C. Lam, Y. Zhu, A. Gokirmak, and H. Silva, “Utilizing Programming Variability in Phase Change Memory Cells for Security”, EM07.04.04, accepted at 2017 MRS Fall Meeting and Exhibit, Boston.
  3. S. Muneer, H. Silva, A. Gokirmak, “Simulations of Reset Operation of Phase Change Memory Devices Based on Semiconductor Physics including the Generation-Transport-Recombination (GTR) of Minority Carriers”, EM 07.07.05, accepted at 2017 MRS Fall Meeting and Exhibit, Boston.
  4. Z. Woods, J. Scoggin, A. Cywar, H. Silva, A. Gokirmak, “Finite Element Modeling of Phase Change Memory Devices—Electro-Thermal Effects and Crystallization-Amorphization Dynamics”, EM07.09.03, accepted at 2017 MRS Fall Meeting and Exhibit, Boston.
  5. J. Scoggin, Z. Woods, A. Cywar, H. Silva, A. Gokirmak, “Finite Element Modeling of Phase Change Memory Devices—Impact of Thermal Boundary Resistances”, EM07.10.01, accepted at 2017 MRS Fall Meeting and Exhibit, Boston.
  6. H. Malboeuf, Z. Woods, J. Scoggin, H. Silva, A. Gokirmak, “Modeling SiO2 Doped Ge2Sb2Te5 Phase-Change Memory Devices”, EM07.10.02, accepted at 2017 MRS Fall Meeting and Exhibit, Boston.
  7. RS. Khan, N. Kan’an, J. Scoggin, Z. Woods, L. Adnane, A. Gorbenko, A. Gokirmak, H. Silva, “Multi-Contact Phase Change Logic Devices”, EM07.13.02, accepted at 2017 MRS Fall Meeting and Exhibit, Boston.
  8. A. Gorbenko, N. Noor, F. Dirisaglik, Y. Zhu, A. Gokirmak, and H. Silva, “Resistance Drift Measurements in On-oxide and Suspended Ge2Sb2Te5 Phase-Change Memory Line Cells”, accepted at 2017 MRS Fall Meeting and Exhibit, Boston.
  9. D. Forte, S. Bhunia, and M. Tehranipoor, Hardware Protection through Obfuscation, Springer, 2017.
  10. F. Rahman, B. Shakya, X. Xu, D. Forte and M. Tehranipoor, “Security Beyond CMOS: Fundamentals, Applications, and Roadmap,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, no. 99, pp. 1-14.
  11. H. Shen, F. Rahman, B. Shakya, X. Xu, M. Tehranipoor, D. Forte, “Poly-Si Based Physical Unclonable Functions”, IEEE Transactions on Very Large Scale Integration Systems, , Vol. PP, No. 99, 2017.
  12. M.T. Rahman, A. Hosey, Z. Guo, J. Carroll, D. Forte, M. Tehranipoor, “Systematic Correlation and Cell Neighborhood Analysis of SRAM-PUF for Robust and Unique Key Generation,” Journal of Hardware and Systems Security (HaSS), Vol. 1, No. 2, October 2017.
  13. H. Wang, Q. Shi, D. Forte, M. Tehranipoor, “Probing Attacks on Integrated Circuits: Challenges and Research Opportunities”, IEEE Design & Test, Vol. 34, No. 5, October 2017.
  14. X. Xu, B. Shakya, M. Tehranipoor, D. Forte, “Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks,” International Conference on Cryptographic Hardware and Embedded Systems (CHES), Sept. 2017.
  15. Z. Guo, J. Di, M. Tehranipoor, D. Forte, “Obfuscation-based Protection Framework Against Printed Circuit Boards Unauthorized Operation and Reverse Engineering”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 3, April 2017
  16. M. Alam, H. Shen, N. Asadi, M. Tehranipoor, D. Forte, “Impact of X-ray Tomography on the Reliability of Integrated Circuits”, IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 17, No. 1, March, 2017.
  17. Z. Guo, X. Xu, M. Tehranipoor, D. Forte, “MPA: Model-assisted PCB Attestation via Board-level RO and Temperature Compensation”, IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), Oct. 2017.
  18. Z. Guo, M. Tehranipoor, D. Forte,”Memory-based Counterfeit IC Detection Framework”, SRC TECHCON, Sept. 2017.
  19. Q. Shi, K. Xiao, D. Forte, M. Tehranipoor, “Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication”, GLSVLSI, May 2017.
  20. Q. Shi, N. Asadizanjani, D. Forte, M.Tehranipoor, “Layout-based Microprobing Vulnerability Assessment for Security Critical Applications,” in GOMACTech, March 2017.
  21. Y. Liu, Y. Xie, and A. Srivastava, “Security in Emerging Fabrication Technologies”, Security Opportunities by Nano Devices and Emerging Technologies / Edited by Mark M. Tehranipoor, Domenic Forte, Garrett Rose, and Swarup Bhunia, CRC Press / Taylor & Francis, USA, 2017
  22. C. Bao, Y. Xie, Y. Liu, and A. Srivastava, “Reverse-Engineering Based Hardware Trojan Detection”, The Hardware Trojan War: Attacks, Myths, and Defenses / Edited by Swarup Bhunia and Mark M. Tehranipoor, Springer, USA, 2017
  23. Y. Liu, Y. Xie, C. Bao, and A. Srivastava, “A Combined Optimization-Theoretic and Side-Channel Approach for Attacking Strong Physical Unclonable Functions”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  24. Y. Liu, Y. Xie, and A. Srivastava, “Neural Trojans”, Proceedings of the 35th IEEE International Conference on Computer Design 2017. IEEE, 2017
  25. D.P. Sahoo, P. H. Nguyen, D. B. Roy, D. Mukhopadhyay, R. S. Chakraborty: Side Channel Evaluation of PUF-Based Pseudorandom Permutation. DSD 2017: 237-243
  26. S.K. Haider, C. Jin, and M. van Dijk. “Advancing the State-of-the-Art in Hardware Trojans Design,” MWSCAS 2017
  27. M.S. Riazi, E.M. Songhori, A.R. Sadeghi, T. Schneider, and F. Koushanfar. “Toward practical secure stable matching.” Proceedings on Privacy Enhancing Technologies 2017, no. 1 (2017): 62-78.
  28. M.S. Riazi, E.M. Songhori, and F. Koushanfar. “PriSearch: Efficient Search on Private Data.” In Proceedings of the 54th Annual Design Automation Conference 2017, p. 14. ACM, 2017.
  29. M.S. Riazi, M. Samragh, and F. Koushanfar. “CAMsure: Secure Content-Addressable Memory for Approximate Search.” ACM Transactions on Embedded Computing Systems (TECS) 2017.
  30. Y. Liu, C. Bao, Y. Xie and A. Srivastava, ” Introducing TFUE: the Trusted Foundry and Untrusted Employee Model in IC Supply Chain Security,” the 50th International Symposium of Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4.
  31. Y. Xie, C. Bao and A. Srivastava, “Security-Aware 2.5D IC Design Flow against Hardware IP Piracy”, IEEE Computer, 2017
  32. Y. Xie, C. Bao, and A. Srivastava. “3D/2.5 D IC-Based Obfuscation.” Hardware Protection through Obfuscation. Springer International Publishing, 2017. 291-314.
  33. Y. Xie, C. Bao, C. Serafy, T. Lu, A. Srivastava, and Mark Tehranipoor. “Security and Vulnerability Implications of 3D ICs.” IEEE Transactions on Multi-Scale Computing Systems 2, no. 2 (2016): 108-122.
  34. Y. Xie, and A. Srivastava. “Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction.” in ACM Design Automation Conference (DAC), 2017.
  35. Chongxi Bao, Ankur Srivastava, “Exploring Timing Side-channel Attacks on Path-ORAMs”, in IEEE Hardware-Oriented Security and Trust (HOST), 2017.
  36. M.T. Arafin, M. Gao, and G. Qu, “VOLtA: Voltage Over-scaling Based Lightweight Authentication for IoT Applications”, Asia and South Pacific Design Automation Conference (ASPDAC’17), Jan., 2017.
  37. A. Cui, Y. Luo, H. Li, G. Qu. “Why Current Secure Scan Designs Fail and How to Fix Them?” Integration, the VLSI Journal. Vol. 56, pp. 105-114, 2017.
  38. X. Chen, G. Qu, A. Cui, and C. Dunbar, “Scan Chain based IP Fingerprint and Identification”, 18th International Symposium on Quality Electronic Design (ISQED’17), March, 2017.
  39. Q. Wang, T. Dunlap, Y. Cho, and G. Qu. “DoS Attacks and Countermeasures on Network Devices,” in IEEE Wireless and Optical Communication Conference (WOCC’17), 2017.
  40. X. Wang, Q. Zhou, Y. Cai, and G. Qu, “An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack”, in IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI’17), 2017.
  41. X. Chen, G. Qu, and A. Cui, “Practical IP Watermarking and Fingerprinting Methods for ASIC Designs”, in IEEE International Symposium on Circuits and Systems (ISCAS’17), 2017.
  42. M. Tehranipoor, U. Guin, and S. Bhunia, “Invasion of the Hardware Snatchers: Fake Hardware Could Open the Door to Malicious Malware and Critical Failure,” IEEE Spectrum, 2017.
  43. B. Shakya, H. Salmani, D. Forte, S. Bhunia, and M. Tehranipoor, “Benchmarking of Hardware Trojans and Maliciously Affected Circuits,” Journal of Hardware and Systems Security (HaSS), 2017.
  44. Z. Guo, X. Xu, M. Tehranipoor, and D. Forte, “FFD: A Framework for Fake Flash Detection,” ACM Design Automation Conference (DAC), June, 2017.
  45. T. Byrant, S. Chowdhury, D. Forte, M. Tehranipoor, N. Maghari, “A Stochastic All-Digital Weak Physically Unclonable Function for Analog/Mixed-Signal Applications”, in IEEE Hardware-Oriented Security and Trust (HOST), 2017.
  46. J. Scoggin, Z. Woods, H. Silva, and A. Gokirmak, “Finite Element Modeling of Ovonic Threshold Switch Controlled Phase Change Memory Devices,” Mat. Res. Soc. Spring Meeting, 2017.
  47. Raihan Sayeed Khan, Nafisa Noor, Aaron Ciardullo, Sadid Muneer, Lhacene Adnane, Faruk Dirisaglik, Adam Cywar, Chung Lam, Yu Zhu, Helena Silva, and Ali Gokirmak; “A Study on Stochasticity in Hexagonal Close Packed Ge2Sb2Te5 Nanowires for Possible Physical Unclonable Function (PUF) Implementation”, Material Research Society Spring Meeting, 2017.
  48. Nafisa Noor, Raihan Sayeed Khan, Sadid Muneer, Lhacene Adnane, Ryanne Ramadan, Faruk Dirisaglik, Adam Cywar, Chung Lam, Yu Zhu, Ali Gokirmak, and Helena Silva; “Short and Long Time Resistance Drift Measurement in Intermediate States of Ge2Sb2Te5 Phase Change Memory Line Cells”, Material Research Society Spring Meeting, 2017.
  49. A. Gokirmak, Z. Woods, J. Scoggin, A. Cywar, H. Silva, “Electrothermal-Dynamic Granular Materials Modeling of Phase Change Memory and Logic Devices” Material Research Society Spring Meeting, 2017
  50. L. Adnane, H. Silva, A. Gokirmak “Seebeck Coefficient, Electrical Resistivity and Derived Thermal Conductivity of Ge2Sb2Te5 Thin Films”, Material Research Society Spring Meeting, 2017
  51. S. Muneer, H. Silva, A. Gokirmak, “Computational Analysis of High Carrier Generation and Its Impact on the Melting and Thermoelectric Effects in Semiconductor Devices”, Material Research Society Spring Meeting, 2017
  52. C. Jin and M. van Dijk, “Secure and Efficient Initialization and Authentication Protocols for SHIELD,” IEEE Transactions on Dependable and Secure Computing, 2017.
  53. S. K. Haider, C. Jin, and M. van Dijk, “Advancing the State-of-the-Art in Hardware Trojans Design,” IEEE Transactions on Dependable and Secure Computing, 2017.
  54. C. Jin, C. Herder, L. Ren, P. H. Nguyen, B. Fuller, S. Devadas, and M. van Dijk, “Practical Cryptographically-Secure PUFs based on Learning Parity with Noise,” demo in IEEE Hardware Oriented Security and Trust (HOST), 2017.
  55. M. Riazi, E. M. Songhori, A. R. Sadeghi, T. Schneider, and F. Koushanfar, “Toward Practical Secure Stable Matching”, Proceedings on Privacy Enhancing Technologies (PETS), vol. 2017, issue 1, 01/2017.

2016

  1. Y. Xie, A. Srivastava, “Mitigating SAT Attack on Logic Locking”, Conference on Cryptographic Hardware and Embedded Systems (CHES), 2016
  2. Y. Xie, C. Bao, C. Serafy, T. Lu, A. Srivastava and M. Tehranipoor, “Security and Vulnerability Implications of 3D ICs”, IEEE Transactions on Multi-Scale Computing Systems, 2016
  3. Y. Liu, Y. Xie, C. Bao, A. Srivastava, “An Optimization-Theoretic Approach for Attacking Physical Unclonable Functions”, in ACM International Conference on Computer-Aided Design (ICCAD) 2016
  4. S. E. Quadir, J. Chen, D. Forte, N. Asadizanjani, S. Shahbazmohamadi, L. Wang, J. Chandy, M. Tehranipoor, “A Survey on Chip to System Reverse Engineering,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 13, No.1, April 2016.
  5. M. M. Alam, M. Tehranipoor, D. Forte, “Recycled FPGA Detection Using Exclusive LUT Path Delay Characterization,” to appear IEEE International Test Conference (ITC), Nov. 2016
  6. B. Shakya, N. Asadi, D. Forte, M. Tehranipoor, “Chip Editor: Leveraging Circuit Edit for Logic Obfuscation and Trusted Fabrication,” to appear IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2016.
  7. H. T. Shen, F. Rahman, B. Shakya, M. Tehranipoor, D. Forte,”Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs)”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2016, pp. 188-193
  8. F. Rahman, D. Forte, and Mark Tehranipoor, “Reliability vs. Security: Challenges and Opportunities for Developing Reliable and Secure Integrated Circuits,” International Reliability Physics Symposium (IRPS), April 2016
  9. Z. Guo, M.T. Rahman, M. Tehranipoor, D. Forte, “A Zero-cost Approach to Detect Recycled Integrated Circuits Using Embedded SRAM,” submitted to Hardware Oriented Security and Trust (HOST) 2016.
  10. Q. Shi, N. Asadizanjani, D. Forte and M. Tehranipoor, “A Layout-driven Framework to Assess Vulnerability of ICs to Microprobing Attacks,” submitted to Hardware Oriented Security and Trust (HOST) 2016.
  11. Q. Shi, D. Forte and M. Tehranipoor, “Analyzing Circuit Layout to Probing Attack,” in Hardware IP Security and Trust: Validation and Test, 2016.
  12. B. Shakya, M. Tehranipoor, S. Bhunia, and F. Forte, “Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation,” in Hardware Protection through Obfuscation, 2016.
  13. Mirhoseini, A., Sadeghi, A. R., and Koushanfar, F., “CryptoML: Secure Outsourcing of Big Data Machine Learning Applications”, IEEE International Symposium on Hardware Oriented Security and Trust(HOST), May, 2016
  14. Zhang, Y., and Koushanfar, F., “Robust Privacy-Preserving Fingerprint Authentication”, in IEEE International Symposium on Hardware Oriented Security and Trust(HOST), May, 2016
  15. Songhori, E. M. M., Zeitouni, S., Dessouky, G., Schneider, T., Sadeghi, A. R., and Koushanfar, F., “GarbledCPU: A MIPS Processor for Secure Computation in Hardware”, ACM Design Automation Conference (DAC), Jun, 2016
  16. Abera, T., Asokan, N., Davi, L., Koushanfar, F., Paverd, A., Sadeghi, A. R., and Tsudik, G., “Things, Trouble, Trust: On Building Trust in IoT Systems”, ACM Design Automation Conference (DAC), Jun, 2016
  17. Hussain, S. U., and Koushanfar, F., “Privacy Preserving Localization for Smart Automotive Systems”, ACM Design Automation Conference (DAC), Jun, 2016
  18. Hussain, S. U., Majzoobi, M., and Koushanfar, F., “A Built-In-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators”, IEEE Transactions on Multi-Scale Computing Systems (TMSCS), vol. 2, issue 99, Jan, 2016
  19. Mirhoseini, A., Rouhani, B. D. D., Songhori, E. M. M, and Koushanfar, F., “Chime: Checkpointing long computations on intermittently energized IoT devices”, IEEE Transactions on Multi-Scale Computing Systems (TMSCS), vol. 2, issue 99, Jan, 2016
  20. J. Scoggin, Z. Woods, A. Cywar, L. Adnane, H. Silva, and A. Gokirmak, “Finite Element Analysis of Grain Boundary Effects in Phase Change Materials via Laser Annealing,” International Semiconductor Device Research Symposium (ISDRS) 2016.
  21. Raihan Sayeed Khan, Nafisa Noor, Aaron Ciardullo, Sadid Muneer, Lhacene Adnane, Faruk Dirisaglik, Adam Cywar, Chung Lam, Yu Zhu, Helena Silva, and Ali Gokirmak; “A Study on Stochasticity in Hexagonal Close Packed Ge2Sb2Te5 Nanowires”, International Semiconductor Device Research Symposium (ISDRS), 2016.
  22. Nafisa Noor, Sadid Muneer, Lhacene Adnane, Raihan Sayeed Khan, Ryanne Ramadan, Faruk Dirisaglik, Adam Cywar, Chung Lam, Yu Zhu, Ali Gokirmak, and Helena Silva, “Pulse-mode Electrical Resistance Trimming of Ge2Sb2Te5 Phase Change Memory (PCM) Line Cells”, International Semiconductor Device Research Symposium (ISDRS), 2016, 3rd best paper award.
  23. C. Herder, L. Ren, M. van Dijk, M. Yu, and S. Devadas, “Trapdoor Computational Fuzzy Extractors and Stateless Cryptographically-Secure Physical Unclonable Functions,” IEEE TDSC, 2016.
  24. Z. Guo, M. Tehranipoor, and D. Forte, “Aging Attacks for Key Extraction on PermutationBased Obfuscation,” IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 2016.
  25. T. Bryant, S. Chowdhury, D. Forte, M. Tehranipoor, and N. Maghari, “A Stochastic Approach to Analog Physical Unclonable Function,” IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 2016.
  26. Y. Xie, C. Bao, Y. Liu, and A. Srivastava. “2.5 D/3D Integration Technologies for Circuit Obfuscation.” In Microprocessor and SOC Test and Verification (MTV), 17th International Workshop on, pp. 39-44. IEEE, 2016.
  27. M.T. Arafin and G. Qu, “Secret Sharing and Multi-User Authentication: From Visual Cryptography to RRAM Circuits”, 26th IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI’16), pp. 169-174, May 2016
  28. P. Qiu, Y. Lyu, J. Zhang, X. Wang, D. Zhai, D. Wang, and G. Qu, “Physical unclonable functions-based linear encryption against code reuse attacks”. IEEE/ACM Design Automation Conference (DAC’16), June 2016
  29. J. Wang, A. Cui, M. Li, G. Qu, and H. Li, “An Ultra-low Overhead LUT-based PUF for FPGA”, 1st IEEE Asian Hardware Security and Trust Symposium (AsianHost’16), December 2016.
  30. Y. Luo, A. Cui, G. Qu, and H. Li, “A New Countermeasure against Scan-Based Side Channel Attacks”, IEEE International Symposium on Circuits and Systems (ISCAS’16), pp. 1722-1725, May 2016.
  31. X. Wang, Q. Zhou, Y. Cai, J. Yang, M. Gao, and G. Qu, “Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers”, 26th IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI’16), pp. 133-136, May 2016.
  32. X. Wang, Q. Zhou, Y. Cai, and G. Qu, “Is the Secure IC Camouflaging Really Secure?”, IEEE International Symposium on Circuits and Systems (ISCAS’16), pp. 1710-1713, May 2016.

2015

  1. B. Shakya, F. Rahman, M. Tehranipoor, D. Forte, “Harnessing Nanoscale Device Properties for Hardware Security”, Microprocessor Test and Verification (MTV), Dec. 2015.
  2. A. Mazady, M.T. Rahman, D. Forte, M. Anwar, “Memristor Nano-PUF A Security Primitive: Theory and Experiment, “ IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS).
  3. U. Guin, D. Forte, M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for protecting Integrated Circuits against Recycling,” IEEE Transactions on VLSI Systems (TVLSI), 2015.
  4. B. Shakya, U. Guin, M. Tehranipoor, D. Forte, “Performance Optimization for On-Chip Sensors to Detect Recycled ICsIEEE International Conference on Computer Design (ICCD), Oct. 2015.
  5. S. Chen, J. Chen, D. Forte, J. Di, M. Tehranipoor, L. Wang, “Chip-level Anti-reverse Engineering using Transformable Interconnects,” IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct. 2015
  6. H. Dogan, D. Forte, M. Tehranipoor, “Aging Analysis for Recycled FPGA Detection,” GOMACTech, March 2015.
  7. C. Jin, X. Xu, W. Burleson, U. Rührmair and M. van Dijk, “PLayPUF: Programmable Logically Erasable PUFs for Forward and Backward Secure Key Management.” Cryptology E-print archive (https://eprint.iacr.org/2015/1052.pdf).
  8. C. Herder, L. Ren, M. van Dijk, M. Yu, and S. Devadas, A Stateless Cryptographically-Secure Physical Unclonable Function,” Cryptology E-print archive.
  9. Marten van Dijk, “Hardware Security and its Adversaries,” 5th International Workshop on Trustworthy Embedded Devices.
  10. M. Gao, J. Zhang, K. Lai, G. Qu, Q. Zhou, and A. Cui, “Reliable and Anti-Cloning PUFs based on Configurable Ring Oscillators”, CAD/Graphics, August 2015.
  11. M.T. Rahman, F. Rahman, D. Forte, M. Tehranipoor, “An Aging-Resistant RO-PUF for Reliable Key Generation”, IEEE Transactions on Emerging Topics in Computing (TETC), September 2015.
  12. M.T. Rahman, F. Rahman, D. Forte, M. Tehranipoor, “A Pair Selection Algorithm for Robust RO-PUF Against Environmental Variations and Aging”, IEEE International Conference on Computer Design (ICCD), Oct. 2015.
  13. Mazady, A.; Rahman, M.T.; Forte, D.; Anwar, M., “Memristor PUF—A Security Primitive: Theory and Experiment,“ in Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol.5, no.2, pp.222-229, June 2015
  14. Shakya, B.; Guin, U.; Tehranipoor, M.; Forte, D., “Performance Optimization for On-Chip Sensors to Detect Recycled ICs”, 33rd IEEE International Conference on Computer Design (ICCD ’15), October 2015
  15. A. Cui, G. Qu, and Y. Zhang, “Dynamic Watermarking on Scan Design for Hard IP Protection with Ultra-low Overhead”, IEEE Transactions on Information Forensics & Security (TIFS), Vol. 10, No. 11, pp. 2298-2313, November 2015. DOI: 10.1109/TIFS.2015.2455338.
  16. J. Zhang, Y. Lin, and G. Qu, “Reconfigurable Binding against FPGA Replay Attacks”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 20, No. 2, Article 33 (20 pages), February 2015.
  17. M.T. Arafin and G. Qu, “RRAM Based User Authentication”, IEEE/ACM International Conference on Computer Aided Design (ICCAD’15), November 2015.
  18. B. Liu, Y. Jin, and G. Qu, “Hardware Design and Verification for Supply Chain Tamper Resistance”, CAD/Graphics, August 2015.
  19. M. Gao, G. Qu, Q. Zhou, and Y. Cai, “Circuit Obfuscation: Motivations, Assumptions, and Techniques”, 19th International Workshop on Logic and Synthesis (IWLS’15), June 2015.
  20. M. T. Arafin, C. Dunbar, G. Qu, N. McDoald, and L. Yan, “A Survey on Memristor Modeling and Security Applications”, 16th International Symposium on Quality Electronic Design (ISQED), March, 2015.
  21. Nafisa Noor, Kadir Cil, Lindsay Sullivan, Sadid Muneer, Faruk Dirisaglik, Adam Cywar, Chung Lam, Yu Zhu, Ali Gokirmak, and Helena Silva, “An experimental study on waveform engineering for Ge2Sb2Te5 phase change memory cells,” MRS, 2015.
  22. Xie, Yang, Chongxi Bao, and Ankur Srivastava, “Security-Aware Design Flow for 2.5D IC Technology,” in Workshop on Trustworthy Embedded Devices (TrustED), 2015.
  23. Bao, Chongxi and Srivastava, Ankur. “3D Integration: New Opportunities in Defense Against Cache-timing Sidechannel Attacks.” Computer Design (ICCD), 2015 33rd IEEE International Conference on. IEEE, 2015.
  24. J. Scoggin, A. Gokirmak, and H. Silva, “A Computational Study on Waveform Engineering for Phase Change Memory,” MRS 2015.
  25. E. M. Songhori, S. U. Hussain, A. Sadeghi, T. Schneider, and F. Koushanfar, “Tinygarble: Highly compressed and scalable sequential garbled circuits,” in IEEE S&P, 2015.

2014

  1. B. Chongxi, D. Forte, and A. Srivastava, On Application of One-class SVM to Reverse Engineering-Based Hardware Trojan Detection”, International Symposium on Quality Electronic Design (ISQED), 2014, Link
  2. M. van Dijk, U. Rührmair, “Protocol attacks on advanced PUF protocols and countermeasures”, Date, 2014
  3. M. van Dijk, U. Ruhrmair, “PUF Interfaces and their Security”, ISVLSI, 2014
  4. K. Xiao, D. Forte, and M. Tehranipoor, “A Novel Built-In Self-Authentication Technique to Prevent Inserting Hardware Trojans,” IEEE Transactions on CAD (TCAD), 2014.
  5. U. Guin, K. Huang, D. DiMase, J. Carulli, M. Tehranipoor, Y. Makris, “Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain,” Proceedings of IEEE, 2014.
  6. U. Guin, D. DiMase, and M. Tehranipoor, “A Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead,” Journal of Electronic Testing: Theory and Applications (JETTA), 2014, Link

2013

  1. A. Markman, B. Javidi, and M. Tehranipoor, “Photon-Counting Security Tagging and Verification Using Optically Encoded QR Codes,” IEEE Photonics Journal, 2013, Link
  2. X. Zhang and M. Tehranipoor, “Design of On-chip Light-weight Sensors for Effective Detection of Recycled ICs,,” IEEE Transactions on VLSI (TVLSI), 2013.